On Delay Fault Testing in Logic Circuits

摘要: Correct operation of a logic circuit requires propagation delays all paths in the to be smaller than intended "clock interval." Random or deterministic tests, conducted at normal clocking rate, can used insure that path manufactured circuits meet specifications. Algorithms, based on five-valued system, accurately calculate detection probability delay faults by random tests as well derive detect are proposed. The results determine test length for desired confidence level testing fault when used, and generate set list used.