Testing oriented analysis of CMOS ICs with opens
作者： W. Maly , P.K. Nag , P. Nigh
DOI: 10.1109/ICCAD.1988.122525
关键词: CMOS 、 Integrated injection logic 、 Electronic circuit 、 Stuck-at fault 、 Fault model 、 Active load 、 Transistor 、 Very-large-scale integration 、 Engineering 、 Electronic engineering
摘要: In a typical approach to VLSI testing, open faults are modeled by the transistor-stuck-open fault model or not explicitly covered at all. It is shown that functional caused opens, i.e. regions with missing material, cannot be well transistor stuck-open. also majority of opens which occur in CMOS static circuits manifest themselves as timing faults. The analysis behavior floating gate indicates it acts weakly 'on' active load, and therefore an detected stuck-fault testing but could monitoring current through power buses. >
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