Method and system for extraction of parasitic interconnect impedance including inductance
作者： Robert G. Mathews , Keh-Jeng Chang , Li-Fu Chang , Martin G. Walker
DOI:
关键词: Static timing analysis 、 Electrical impedance 、 Parasitic element 、 Integrated circuit 、 Inductance 、 Equivalent series inductance 、 Integrated circuit layout 、 Computer science 、 Parasitic extraction 、 Electronic engineering
摘要: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. extractor analyzes structures within selected distance conductor circuit and determines values using library. Using this system, impedances, including inductance, may be extracted layout, thus allowing more accurate modeling timing analysis layout to obtained.
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