Extraction of parasitic circuit elements in a PEBB for application in the virtual test bed
作者： B. Beker , J.L. Hudgins , J. Coronati , B. Gillett , S. Shekhawat
关键词: Solver 、 Inductance 、 Parasitic capacitance 、 Parasitic element 、 Virtual prototyping 、 Engineering 、 Electronic engineering 、 Capacitance 、 Power electronics 、 Electrical element
摘要: A numerical procedure for extracting parasitic circuit elements using a quasi-static field solver, as part of the virtual test bed (VTB), is discussed. The inductance and capacitance values obtained from model are compared to measured low-inductance power electronic building block (PEBB) module, designed constructed at Harris Semiconductor.
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