作者: Joydeep Mitra , Peng Yu , David Z. Pan
关键词: Design for manufacturability 、 Lithography 、 Design closure 、 Engineering 、 Optical proximity correction 、 CPU time 、 Routing (electronic design automation) 、 Physical design 、 Radar 、 Electronic engineering
摘要: This paper attempts to reconcile the growing interdependency between nanometer lithography and physical design. We first introduce concept of hotspots edge placement error (EPE) map measure overall printability manufacturing effort. then adapt fast simulation models generate EPE map. Guided by map, we develop effective RET-aware detailed routing (RADAR) techniques that can handle full-chip capacity enhance while maintaining other design closure. RADAR is implemented in an industry strength router, tested using some 65nm designs. Our experimental results show achieve up 40% reduction with reasonable CPU time.