A novel memoryless AES cipher architecture for networking applications
作者： Yeong-Kang Lai , Li-Chung Chang , Lien-Fei Chen , Chi-Chung Chou , Chun-Wei Chiu
DOI: 10.1109/ISCAS.2004.1329008
关键词: Encryption 、 XOR gate 、 Cryptography 、 Computer science 、 Hardware architecture 、 Embedded system 、 Advanced Encryption Standard 、 Pipeline (computing) 、 Key schedule
摘要: In this paper, we present a novel fast S-box algorithm without lookup table method, and optional hardware architecture for MixColumn Inverse module with only 5 XOR gate delay. We use on-the-fly key schedule both encryption decryption. Furthermore, implement memoryless AES cipher proposed by adopting pipeline method to obtain high throughput as 1.454 Gbits/sec under 125 MHz using 0.25 m CMOS technology the cost is about 80 K counts. According our knowledge, first including decryption function.
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