An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES
作者： Chung-Yi Li , Chih-Feng Chien , Jin-Hua Hong , Tsin-Yuan Chang
关键词:
摘要: MixColumns/InvMixColumns dominates both the logic resource and critical delay in advanced encryption standard (AES) hardware implementation with direct mapping S-boxes. The proposed decomposition method optimizes area of integrated circuit. Theoretically, short-path circuit reduces up to 42% same 5 XOR gates (Y.-K. Lai et al, 2004) path. When synthesized a TSMC 0.18 mum CMOS technology, has top performance measured AT AT2.
acm.org 
sci-hub.se 参考文章(18)
Vincent Rijmen, Efficient Implementation of the Rijndael S-box ,(2000)
Viktor Fischer, Realization of the Round 2 AES Candidates using Altera FPGA ,(2000)
Kris Gaj, Pawel Chodowiec, Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware. AES Candidate Conference. pp. 40- 54 ,(2000)
Yeong-Kang Lai, Li-Chung Chang, Lien-Fei Chen, Chi-Chung Chou, Chun-Wei Chiu, A novel memoryless AES cipher architecture for networking applications international symposium on circuits and systems. ,vol. 4, pp. 333- 336 ,(2004) , 10.1109/ISCAS.2004.1329008
Paweł Chodowiec, Kris Gaj, Very Compact FPGA Implementation of the AES Algorithm cryptographic hardware and embedded systems. pp. 319- 333 ,(2003) , 10.1007/978-3-540-45238-6_26
Yu-Jung Huang, Yang-Shih Lin, Kuang-Yu Hung, Kuo-Chen Lin, Efficient Implementation of AES IP asia pacific conference on circuits and systems. pp. 1418- 1421 ,(2006) , 10.1109/APCCAS.2006.342467
Hua Li, Z. Friggstad, An efficient architecture for the AES mix columns operation international symposium on circuits and systems. pp. 4637- 4640 ,(2005) , 10.1109/ISCAS.2005.1465666
A.J. Elbirt, W. Yip, B. Chetwynd, C. Paar, An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists IEEE Transactions on Very Large Scale Integration Systems. ,vol. 9, pp. 545- 557 ,(2001) , 10.1109/92.931230
Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu, A configurable AES processor for enhanced security Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05. ,vol. 1, pp. 361- 366 ,(2005) , 10.1145/1120725.1120870
Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh, A Compact Rijndael Hardware Architecture with S-Box Optimization international conference on the theory and application of cryptology and information security. ,vol. 2248, pp. 239- 254 ,(2001) , 10.1007/3-540-45682-1_15