Efficient Implementation of AES IP
作者： Yu-Jung Huang , Yang-Shih Lin , Kuang-Yu Hung , Kuo-Chen Lin
DOI: 10.1109/APCCAS.2006.342467
关键词:
摘要: The AES IP with different architectures implemented using ASIC and FPGA are presented in this paper. For design, the performance of has been evaluated by comparing its area/power/delay, synthesized TSMC 0.35 mum cell library 0.18 library. estimation implementation Altera Xilinx platforms also presented. hardware results proposed architecture Mixcolumn/preprocess InvMixcolumn to perform Mixcolumn/InvMixcolumn transformation less area cost as compared previous relevant architecture. Due I/O bottlenecks between host processor a stand alone module, reconfigurable bandwidth sharing is enhance system
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