High-performance designs of AES transformations
作者： Ning Chen , Zhiyuan Yan
DOI: 10.1109/ISCAS.2009.5118410
关键词:
摘要: Both area and throughput are significant for hardware implementations of the Advanced Encryption Standard (AES). Previous works mostly focused on without providing full control critical path delay (CPD), which ultimately determines throughput. To address this issue, we propose a delay-aware common subexpression elimination (DACSE) algorithm that is novel in two aspects: it not only takes advantage implicit subexpressions to further reduce area, but also minimizes while satisfying any feasible CPD requirement. Using our DACSE algorithm, high-performance designs major transformations AES, MixColumns SubBytes. Compared with prior works, achieve same or shorter CPDs smaller gate counts.
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