A configurable AES processor for enhanced security
作者： Chih-Pin Su , Chia-Lung Horng , Chih-Tsun Huang , Cheng-Wen Wu
关键词:
摘要: We propose a configurable AES processor for extended-security communication. The proposed architecture can provide up to 2/sup 19/ different block cipher schemes within reasonable hardware cost. Data be encrypted not only with secret keys and initial vectors, but also by ciphers during the A novel on-the-fly key expansion design is 28-, 192-, 256-bit keys. Our unified run both original algorithm extended algorithm. has been fabricated 0.25/spl mu/m CMOS process, silicon area of 6.93mm/sup 2/ - about 200.5K equivalent gates. Under 66MHz clock, throughput rate ECB CBC operation modes are 844.8Mbps, 704Mbps, 603.4Mbps 128-bit, 192-bit, keys, respectively.
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