作者: Yoshiharu Tosaka , Hideo Ehara , Mitsuaki Igeta , Taiki Uemura , Hideki Oka
DOI: 10.1109/IEDM.2004.1419339
关键词: Static random-access memory 、 Soft error 、 Integrated circuit 、 CMOS 、 Integrated circuit design 、 Electronic engineering 、 Electronic circuit 、 Error detection and correction 、 Reliability (semiconductor) 、 Electrical engineering 、 Engineering
摘要: Characteristics of soft errors (SEs) in 90/130 nm CMOS circuits were comprehensively investigated by high energy neutron- and alpha-accelerated tests. Process dependence on SEs latch due to neutrons alpha-ray investigated. Error patterns multiple-bit SRAMs their impacts ECC design also discussed.