Biasing circuit and method to achieve compaction and self-limiting erase in flash EEPROMs
作者： Wayland B. Holland , Cetin Kaya , Rabah Mezenner
DOI:
关键词: Flash (photography) 、 Electrical engineering 、 Biasing 、 Self limiting 、 Compaction 、 Drain-induced barrier lowering 、 Voltage source 、 Voltage 、 Threshold voltage 、 Materials science
摘要: The erasing method of this invention results in a relatively narrow distribution threshold voltages when used to flash erase group floating-gate-type memory cells (10). Each cell includes control gate (14), source (11 ) and drain (12). comprises connecting the gates (14) control-gate voltage (Vg), sources (Vs) having higher potential than the, (Vg) drains (12) subcircuit (DS) having, at least one embodiment, (Vd) between (Vs), sufficiently low impedance allow current flow (11) time during operation. allows for optimum part may be fed back arrest process an point.
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