Method and apparatus for managing packet fifos
作者： Kevin John Gildea , Peter Heiner Hochschild , Yun-Pong Huang
DOI:
关键词: External Bus Interface 、 Back-side bus 、 Address bus 、 IEBus 、 Embedded system 、 Computer science 、 Local bus 、 Control bus 、 System bus 、 Computer hardware 、 Bus network
摘要: A method and apparatus for transferring data between a main processor its memory packet switch includes first bus coupled to the memory, bidirectional first-in-first-out (FIFO) buffer second bus. The FIFO having port connected further communications processor, bus, operatively direct access (DMA) engine buffer, interface, switch, interfacing switch. packets are communicated of in accordance with communication protocol. DMA engines transfer independently each other.
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