System-on-Chip-Challenges in the Deep-Sub-Micron Era
作者： Jan M. Rabaey
关键词: Network on a chip 、 Concurrency 、 Computer science 、 Software 、 Platform-based design 、 Robustness (computer science) 、 Risk analysis (engineering) 、 Power management 、 System on a chip 、 Massively parallel
摘要: Continued scaling of semiconductor technology has created hopes for true system-on-a-chip integration; that is, the integration a complete system on single die silicon. Yet, this prospect is seriously challenged by cost considerations. Solutions maximize flexibility and re-use may be only way to address concerns, but necessitate offsetting energy performance penalty comes with software solutions through an aggressive use concurrency. A truly network-based solution option resolve many issues come massive parallelism such as reliability, robustness, synchronization, power management. This chapter presents insight in some approaches methodologies are currently under development at Gigascale Systems Research Center [GSRC].
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