作者: H. Zhang , V. Prabhu , V. George , M. Wan , M. Benes
DOI: 10.1109/4.881217
关键词:
摘要: A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. 5.2 mm/spl times/6.7 mm prototype processor, targeted for voice compression, is implemented in a 0.25-/spl mu/m 6-metal CMOS process, consumes 1.8 mW an average operation rate 40 MHz. It combines embedded microprocessor with array computational units different granularities, connected by hierarchical interconnect network.