Fabrication and Dielectric Breakdown of 3C-SiC/SiO 2 MOS Capacitors
作者： Fan Li , Song Qiu , Mike R. Jennings , Phil A. Mawby
DOI: 10.1109/DEMPED.2019.8864836
关键词: Annealing (metallurgy) 、 Silicon 、 Logic gate 、 Voltage 、 Optoelectronics 、 Fabrication 、 Dielectric strength 、 Materials science 、 Gate oxide 、 Capacitor
摘要: MOS capacitors with thick (≈65nm) SiO 2 gate oxide were fabricated on 3C-SiC/Si substrates and characterised (CV IV) at room temperature to study the state of art 3C-SiC/SiO interface. A low interface trap density ~2.5×1011cm−2eV−1was obtained N O annealed devices using high-low method. Gate was biased elevated voltage distribution cumulative failed studied. Two failure mechanisms identified mechanism 1 dominating 6-8.5MV/cm range, becoming more obvious above S.5MV/cm. The rate a diameter 100µm 3MV/cm estimated be ~3450 PPM.
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