3D non-volatile memory array with sub-block erase architecture
作者： Teng-Hao Yeh , Kuo-Pin Chang
DOI:
关键词: NAND gate 、 Block (programming) 、 Computer science 、 Reference line 、 Parallel computing 、 Control circuit 、 Set (abstract data type) 、 Line (text file) 、 Non-volatile memory 、 Computer hardware
摘要: A memory device has a divided reference line structure which supports sub-block erase in NAND including plurality of blocks. Each block the blocks is coupled to set Y lines, where two or more. includes single select (RSL), operable connect each corresponding lines. control circuit can be included on configured for an operation selected block.
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