Vertical gate stacked nand and row decoder for erase operation
作者： Hyoung Seub Rhie
DOI:
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摘要: A three-dimensional integrated circuit non-volatile memory array includes a with multiple vertical gate NAND cell strings formed in different layers over substrate which share common set of word lines, where groupings between dedicated pairings source line structures and bit form separately erasable blocks are addressed erased by applying an erase voltage to the structure block being while ground other high pass array.
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