A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

摘要: We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL pitch=75nm, 64-WL string 63% array core efficiency. This is the first time that a can be successfully scaled to below 3Xnm in one lateral dimension, thus stack device already provides very cost effective technology lower than conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve manufacturability layout twists even/odd BL's (and pages) opposite direction (split-page BL) adopted. allows island-gate SSL devices [1] and metal interconnections laid out double pitch, creating much larger process window for scaling; (2) A novel staircase contact formation method using binary sum of only M lithography etching steps achieve 2M contacts. not precise landing tight-pitch contacts, but also minimizes cost. have fabricated TFT BE-SONOS charge-trapping device. The characteristics including reading, programming, inhibit, block erase are demonstrated.