Nonvolatile memory with split substrate select gates and hierarchical bitline configuration

摘要: Generally, the present disclosure provides a non-volatile memory device having hierarchical bitline structure for preventing erase voltages applied to one group of cells array from leaking other groups in which erasure is not required. Local bitlines are coupled each cells. Each local can be selectively connected global during read operations selected group, and all disconnected an operation when specific erasure. Select devices electrically connecting have bodies that isolated those