Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques

摘要: The evolution of deep submicron technologies allows the development increasingly complex Systems on a Chip (SoC). However, this is rendering less viable some well-established design practices. Examples are use multi-point communication architectures (e. g. busses) and designing fully synchronous systems. In addition, power dissipation becoming one main concerns due e. to increasing mobile products. An alternative overcome such problems adopting Networks (NoCs) supporting globally asynchronous locally (GALS) system design. This work proposes GALS router with associated control techniques, which enables low SoC in contrast previous works centered attention reduction processing elements instead. paper describes interface employed mechanism. results obtained from simulation at RTL level timing show that, even when submitted large rates traffic injection, proposed NoC displays significant switching activity consequently dissipation.