作者: A.M. Nielsen , D.W. Matula , C.N. Lyu , G. Even
DOI: 10.1109/12.822562
关键词: Parallel computing 、 IEEE floating point 、 Floating point 、 Packet forwarding 、 Computer science 、 Operand 、 Operand forwarding 、 Multiplier (economics) 、 Adder 、 Binary number 、 Rounding
摘要: This paper presents a floating-point addition algorithm and adder pipeline design employing packet forwarding paradigm. The format the proposed algorithms constitute new paradigm for handling data hazards in deeply pipelined pipelines. rounding employ four stage execution phase with each suitable implementation short clock period, assuming about 15 logic levels per cycle. first two cycles are related to proper focus of this paper. last perform have been covered by D.W. Matula A.M. Nielsen (1997). accepts one operand standard binary formal at start cycle one. second is represented format: namely, it divided into parts: sign bit, exponent string, principal part significant, carry-round packet. three parts input two. result output formats that both represent rounded as required IEEE 754 standard. end allow an effective latency cycles. also retirement register. thus available or cooperating multiplier accepting operand. successive dependent operations while perceiving compatibility.