作者: D.C. Matula , A.M. Nielsen
DOI: 10.1109/ARITH.1997.614889
关键词:
摘要: The paper presents the foundations for a packet forwarding floating point format and design of rounder ensuring compatibility between standard binary IEEE 754 format. related addition multiplication algorithms described in this series propose new ALU pipeline paradigm handling data hazards pipelined operations. execution phases adder multiplier pipelines are illustrated by proposed implementation having four stages. latter two stages each employ herein. phase intended to map logic designs, with only some fifteen levels per stage allowing be mapped reasonably short cycles. provides input output cycle effective latency cooperating pipelines. designs we cut half reduce stall cycles factor three compared conventional processing dependent speedup is realized, preservation compatibility.