Multiple path IEEE floating-point fused multiply-add
作者： P.-M. Seidel
DOI: 10.1109/MWSCAS.2003.1562547
关键词:
摘要: We propose optimizations for the IEEE floating-point fused multiply-add operation by considering multiple exclusive parallel computation paths in implementation. For proposed design we can show a significant performance improvement over conventional implementations. Considering variable latency implementation allows further reduction of average latency.
sci-hub.se 参考文章(21)
T. Lang, J.D. Bruguera, Floating-point fused multiply-add with reduced latency international conference on computer design. pp. 145- 150 ,(2002) , 10.1109/ICCD.2002.1106762
M. Putrino, R.M. Jessani, Comparison of single- and dual-pass multiply-add fused floating-point units IEEE Transactions on Computers. ,vol. 47, pp. 927- 937 ,(1998) , 10.1109/12.713312
Silva M. Mueller, On the scheduling of variable latency functional units acm symposium on parallel algorithms and architectures. pp. 148- 154 ,(1999) , 10.1145/305619.305635
D.C. Matula, A.M. Nielsen, Pipelined packet-forwarding floating point. I. Foundations and a rounder symposium on computer arithmetic. pp. 140- 147 ,(1997) , 10.1109/ARITH.1997.614889
Shijun Jiang, Zeqi Pan, M. Dagenais, R.A. Morgan, K. Kojima, Influence of external optical feedback on threshold and spectral characteristics of vertical-cavity surface-emitting lasers IEEE Photonics Technology Letters. ,vol. 6, pp. 34- 36 ,(1994) , 10.1109/68.265881
D.G. Deppe, D.L. Huffaker, Tchang-Hun Oh, Hongyu Deng, Qing Deng, Low-threshold vertical-cavity surface-emitting lasers based on oxide-confinement and high contrast distributed Bragg reflectors IEEE Journal of Selected Topics in Quantum Electronics. ,vol. 3, pp. 893- 904 ,(1997) , 10.1109/2944.640643
Roger King, Rainer Michalzik, Christian Jung, Martin Grabherr, Franz Eberhard, Roland Jaeger, Peter Schnitzer, Karl J. Ebeling, Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects High-power lasers and applications. ,vol. 3286, pp. 64- 71 ,(1998) , 10.1117/12.305445
H. Sharangpani, H. Arora, Itanium processor microarchitecture IEEE Micro. ,vol. 20, pp. 24- 43 ,(2000) , 10.1109/40.877948
F. P. O'Connell, S. W. White, POWER3: the next generation of PowerPC processors Ibm Journal of Research and Development. ,vol. 44, pp. 873- 884 ,(2000) , 10.1147/RD.446.0873
Peter-Michael Seidel, High-speed redundant reciprocal approximation Integration. ,vol. 28, pp. 1- 12 ,(1999) , 10.1016/S0167-9260(99)00008-5