Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic array

摘要: Thin-film transistor (TFT) circuits are facing the challenges of unipolar device, process variation, and yield problems, which can be addressed by pseudo-CMOS logic array with multi-layer interconnect. However, existing design methodology does not take mechanical strain temperature into consideration may seriously affect carrier mobility TFT thus performance whole circuits. This paper presents a novel cell mapping algorithm including intrarow step inter-row for flexible to mitigate influence. Experimental results indicate that there is more than 40% improvement in critical path delay at best case proposed algorithm.