作者: Chao-Hsuan Hsu , Chester Liu , En-Hua Ma , James Chien-Mo Li
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摘要: This paper presents a static timing analyzer for flexible TFT circuits (STAF). Gate delay models are first characterized by SPICE simulation as function of load capacitance and mobility. A block-based STA algorithm is then applied to identify the longest path shortest change in different regions under bending. STAF plots maps that show "bending hot spots" which, when bended, significantly circuit timing. Experimental results on ISCAS'89 benchmark can increase up 32% single region bended. What worse, be 9%, which cannot simply fixed reduced clock speed. provides important information designers.