Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction
作者： Tatsuya Yamamoto , Kazuei Hironaka , Yuki Hayakawa , Masayuki Kimura , Hideharu Amano
DOI: 10.1007/978-3-642-19475-7_24
关键词: Computer hardware 、 Overhead (computing) 、 Efficient energy use 、 Reduction (complexity) 、 Alpha (programming language) 、 Filter (video) 、 Dissipation 、 Energy (signal processing) 、 Chip 、 Parallel computing 、 Computer science
摘要: This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Processors. Either high or low supply is dynamically selected at each PE the context-by-context basis. We designed part array and applied this technique. A test chip fabricated in 65nm technology operated successfully. Detailed simulations revealed that reduction hindered by overhead due when we use even lower VDD. propose mapping optimization algorithm "PFCM" minimize overhead. PFCM reduced 90.8% thereby up 12.5% running sepia filter, alpha blender Laplacian filter programs.
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