Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures
作者： Thomas Schweizer , Tobias Oppold , Julio Oliveira Filho , Sven Eisenhardt , Kai Blocher
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摘要: In dynamically reconfigurable processors, different contexts as well data paths within one context usually vary in their execution time. Voltage scaling offers the ability to utilize this variation reduce power consumption. paper, we propose a dual-VDD processor architecture which utilizes varying time dynamic consumption without adapting clock frequency. Gate-level simulations reveal that proposed reduces of processing element up 22.1% and total 10.5% compared single voltage instance.
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