Low-Power Reconfigurable Processor Utilizing Variable Dual $V_{\rm DD}$
作者： Jianfeng Zhu , Leibo Liu , Shouyi Yin , Shaojun Wei
DOI: 10.1109/TCSII.2013.2251940
关键词: Static timing analysis 、 Energy conservation 、 Efficient energy use 、 Power gating 、 Low-power electronics 、 Embedded system 、 CMOS 、 Arithmetic logic unit 、 Power analysis 、 Engineering
摘要: The dual-VDD technique has already been employed in reconfigurable processors to improve energy efficiency. In this brief, a variable method is proposed reduce power consumption further through varying the level of lower VDD (VDDL) according application on processor. It finds out optimum VDDL mainly based utilization times all arithmetic logic unit operations by application. estimation, analysis technology and architecture highly required as well. Static timing were performed RPU, processor designed 65-nm CMOS technology. estimated that can its array 32% average for applications GPS, MPEG2, H.264, audio video coding standard (AVS). If fixed at 0.6-0.75 V, reduction rate will be 15% less average. area penalty than 3%.
sci-hub.se 参考文章(12)
Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins, ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix field-programmable logic and applications. pp. 61- 70 ,(2003) , 10.1007/978-3-540-45234-8_7
Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami, Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction Lecture Notes in Computer Science. pp. 230- 241 ,(2011) , 10.1007/978-3-642-19475-7_24
Thomas Schweizer, Tobias Oppold, Julio Oliveira Filho, Sven Eisenhardt, Kai Blocher, Wolfgang Rosenstiel, Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures field-programmable technology. pp. 381- 384 ,(2007) , 10.1109/FPT.2007.4439291
H. Singh, Ming-Hau Lee, Guangming Lu, F.J. Kurdahi, N. Bagherzadeh, E.M. Chaves Filho, MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications IEEE Transactions on Computers. ,vol. 49, pp. 465- 481 ,(2000) , 10.1109/12.859540
Tzu-Der Chuang, Pei-Kuei Tsung, Pin-Chih Lin, Lo-Mei Chang, Tsung-Chuan Ma, Yi-Hau Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen, A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applications 2010 IEEE International Solid-State Circuits Conference - (ISSCC). pp. 330- 331 ,(2010) , 10.1109/ISSCC.2010.5433908
Stephen Bijansky, Adnan Aziz, TuneFPGA: post-silicon tuning of dual-Vdd FPGAs design automation conference. pp. 796- 799 ,(2008) , 10.1145/1391469.1391672
Yan Lin, Lei He, Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction design, automation, and test in europe. pp. 1- 6 ,(2007) , 10.1109/DATE.2007.364665
T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Sakurai, T. Furuyama, Variable supply-voltage scheme for low-power high-speed CMOS digital design IEEE Journal of Solid-state Circuits. ,vol. 33, pp. 454- 462 ,(1998) , 10.1109/4.661211
D. Rossi, F. Campi, A. Deledda, S. Spolzino, S. Pucillo, A heterogeneous digital signal processor implementation for dynamically reconfigurable computing custom integrated circuits conference. pp. 641- 644 ,(2009) , 10.1109/CICC.2009.5280747
Fei Li, Yan Lin, Lei He, Vdd programmability to reduce FPGA interconnect power international conference on computer aided design. pp. 760- 765 ,(2004) , 10.1109/ICCAD.2004.1382678