A heterogeneous digital signal processor implementation for dynamically reconfigurable computing

摘要: This paper describes a System On Chip (SoC) implementation of heterogeneous multi-core digital signal processor, that exploits different flavours reconfigurable computing, merged together in highly-parallel on chip interconnect utilized for data, configuration and control. The device incorporates an embedded field programmable gate array (eFPGA), mid-grain intensive-computation datapath (DREAM), coarse grain (PACT XPP) integrated 3 independent clock islands. fourth global island ARM processor manages communication, synchronization between the cores. joins flexibility three run-time configurable engines with dynamic frequency scaling techniques enabling performance/power tuning. SoC was implemented 90 nm CMOS technology is 110mm2. It performs several GOP/S, depending operation granularity.