A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing

摘要: This paper describes a System on Chip implementation of reconfigurable digital signal processor. The device is suitable for execution wide range applications exploiting balanced mix heterogeneous fabrics merged together by flexible and efficient communication infrastructure based 64-bit Network On Chip. SoC combines fine grain embedded FPGA, mid configurable processor coarse array. An ARM featuring resident operating system the supervisor, managing communication, synchronization reconfiguration mechanisms. computational model enables programmer to manage high level global data complex processing through processor, while allocating most critical kernels engines. has been fabricated in 90-nm technology, die area being 110 mm2; it integrates 97 million transistors peak power consumption 2.5 W. In order demonstrate proposed capabilities real test case, video surveillance motion detection application was implemented SoC. When running this application, proved able deliver 120 GOPS dissipating 1.45