作者: Cathal G. Phelan , Ashish Pancholy , Simon J. Lovett
DOI:
关键词: Physical address 、 Random access memory 、 Address bus 、 Computer science 、 Address space 、 Periodic function 、 Computer hardware 、 Single cycle 、 Transfer (computing)
摘要: A circuit including an address bus providing random addresses for a access memory array, and register configured to receive, store or transfer (i) first from the in response periodic signal transition (ii) second transition, wherein transitions occur within single cycle, are preferably complementary each other. In further embodiment, invention concerns having information predecoder at least partially decode bus, decoded cycle; postdecoder activate receiving register.