作者: J. Bastos , M. Steyaert , A. Pergoot , W. Sansen
关键词: PMOS logic 、 Threshold voltage 、 Transistor 、 Inverse 、 CMOS 、 Square root 、 Optoelectronics 、 NMOS logic 、 Electronic engineering 、 Materials science 、 Communication channel
摘要: The characterization of transistor mismatch in a standard 0.7 µm CMOS technology is presented. A new method for matching parameter extraction has been used. Mismatch parameters based on measurements 10000 nMOS and pMOS transistors have extracted. It observed that the threshold voltage linear dependency inverse square root effective channel area no longer holds length. An extended model physical causes proposed. Contrary to established theory, it with length below 1 less current than what predicted by relationship area.