Hierarchical design of integrated circuits with multi-patterning requirements
作者： Brian Dreibelbis , John P. Dubuque , Jeffrey G. Hemmett , Chandramouli Visweswariah , Natesan Venkateswaran
DOI:
关键词: Executable 、 One-to-one 、 Hierarchical design 、 Integrated circuit 、 Computer science 、 Engineering drawing
摘要: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented computer infrastructure having executable code tangibly embodied readable storage medium programming instructions operable to assign color each pattern shape first cell, second characterize quantities interest the determine that colors assigned all one mappable cells, using characterized model cell.
lens.org 参考文章(21)
Feng-Ming Chang, Chang-Ta Yang, Ping-Wei Wang, Min Cao, Multiple patterning technology method and system for achieving minimal pattern mismatch ,(2011)
Hiroshi Shimomura, Kyoko Hirata, Circuit simulation method, circuit simulation device, and circuit simulation program and computer readable storage medium onto which the program is stored ,(2002)
Prashant B. Phatak, Combinatorial process optimization methodology and system ,(2011)
John Mclntosh, Scott Nagel, Scott Jessen, Substrate topography compensation at mask design: 3D OPC topography anchored ,(2002)
Pieter J. Woltgens, Ulrich A. Finkler, Fook-Luen Heng, Gregory A. Northrop, Leon Stok, James A. Culp, Mark A. Lavin, John M. Cohn, Jin Fuw Lee, Nakgeuon Seong, Lars W. Liebmann, Rama N. Singh, Physical design system and method ,(2004)
Justin Ghan, Abdurrahman Sezginer, System and method for model based multi-patterning optimization ,(2011)
Shunsuke Koshihara, Ryoichi Matsuoka, Mihoko Kijima, Hitoshi Komuro, Method for measuring sample and measurement device ,(2009)
Yuan-Te Hou, Fang-Yu Fan, Ken-Hsien Hsieh, Huang-Yu Chen, Lee-Chung Lu, Li-Chun Tien, Lee Fung Song, Ru-Gun Liu, Wen-Chun Huang, Method and apparatus for achieving multiple patterning technology compliant design layout ,(2010)
C. P. Ausschnitt, P. Dasari, Multi-patterning overlay control Proceedings of SPIE. ,vol. 6924, pp. 692448- ,(2008) , 10.1117/12.772865
Kwangok Jeong, Andrew B. Kahng, Rasit O. Topaloglu, Assessing chip-level impact of double patterning lithography international symposium on quality electronic design. pp. 122- 130 ,(2010) , 10.1109/ISQED.2010.5450394