Substrate topography compensation at mask design: 3D OPC topography anchored

摘要: A semiconductor manufacturing method analyzes topography variations in three dimensions for each photolithographic level and determines critical dimension (CD) bias compensation as inputs to mask layout creation. Accurate predictions of variation a specific design are made at the die using known pattern density CMP planarization length characteristics pattern. Exhaustive characterization photoresist response de-focus is determined by artificially expanding loss CD through focus. Mask an expanded range focus over all lines spaces maintained within specification. 3D data obtained determine height component pixel location die. The resulting OPC model then utilized