Fault Injection Based Channel Allocation Of Noc Architecture For Ldpc Decoders
作者： N.Ashok kumar , , P Nagarajan
关键词: ModelSim 、 Computer science 、 Distributed computing 、 Network interface 、 Network planning and design 、 Modular design 、 Fault injection 、 Computer architecture 、 Routing (electronic design automation) 、 Network packet 、 Verilog
摘要: Network-on-chip (NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols packet- switched networks which consist of routers, links, network interfaces on a predefined topology. In this Project ,we design network-on-chip is based Cartesian environment. This project proposes new topology uded to reduce routing time, it an suitable alternate implementation. cartesian Network-On-Chip can be modelled using Verilog HDL simulated Modelsim software&Quartus II. Keywords: Network-on-Chip (NoC), Routing, Switching, Cut-through,Cartesian
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