A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors
作者： D. El-Damak , S. Bandyopadhyay , A. P. Chandrakasan
DOI: 10.1109/ISSCC.2013.6487776
关键词: Capacitor 、 Electronic engineering 、 Electrical engineering 、 Switched capacitor 、 Inductor 、 Filter capacitor 、 Charge pump 、 Ferroelectric capacitor 、 Parasitic capacitance 、 Film capacitor 、 Engineering
摘要: Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation systems by powering circuit blocks at minimum voltage that meets desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate an integrated conversion solution eliminates need inductors [2,3]. However, SC efficiency is limited conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to overhead control circuit. Reconfigurable supporting multi-gain settings been proposed allow across wide output range [2,4]. Also, High density deep trench capacitors with low capacitance utilized [5] achieving peak 90%. In this work, we exploit on-chip ferroelectric (Fe-Caps) charge transfer owing their high and extremely [6]. achieved combining Fe-Caps setting converter reconfigurable architecture dynamic gain selection.
sci-hub.se 参考文章(8)
Gerard Villar Pique, A 41-phase switched-capacitor power converter with 3.8mV output ripple and 81% efficiency in baseline 90nm CMOS international solid-state circuits conference. pp. 98- 100 ,(2012) , 10.1109/ISSCC.2012.6176892
Hanh-Phuc Le, Michael Seeman, Seth R. Sanders, Visvesh Sathe, Samuel Naffziger, Elad Alon, A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm 2 at 81% efficiency international solid-state circuits conference. pp. 210- 211 ,(2010) , 10.1109/ISSCC.2010.5433981
Yogesh Ramadass, Ayman Fayed, Baher Haroun, Anantha Chandrakasan, A 0.16mm 2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS international solid-state circuits conference. pp. 208- 209 ,(2010) , 10.1109/ISSCC.2010.5433984
B.H. Calhoun, A. Chandrakasan, Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm CMOS international solid-state circuits conference. pp. 300- 599 ,(2005) , 10.1109/ISSCC.2005.1493988
Leland Chang, Robert K. Montoye, Brian L. Ji, Alan J. Weger, Kevin G. Stawiasz, Robert H. Dennard, A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm 2 symposium on vlsi circuits. pp. 55- 56 ,(2010) , 10.1109/VLSIC.2010.5560267
Tom Van Breussegem, Michiel Steyaert, A 82% efficiency 0.5% ripple 16-phase fully integrated capacitive voltage doubler symposium on vlsi circuits. pp. 198- 199 ,(2009)
Yogesh K. Ramadass, Anantha P. Chandrakasan, Voltage Scalable Switched Capacitor DC-DC Converter for Ultra-Low-Power On-Chip Applications power electronics specialists conference. pp. 2353- 2359 ,(2007) , 10.1109/PESC.2007.4342378
H.P. McAdams, R. Acklin, T. Blake, X.-H. Du, J. Eliason, J. Fong, W.F. Kraus, D. Liu, S. Madan, T. Moise, S. Natarajan, N. Qian, Y. Qiu, K.A. Remack, J. Rodriguez, J. Roscher, A. Seshadri, S.R. Summerfelt, A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process IEEE Journal of Solid-state Circuits. ,vol. 39, pp. 667- 677 ,(2004) , 10.1109/JSSC.2004.825241