作者: Loai G. Salem , Patick P. Mercier
DOI: 10.1109/ISSCC.2014.6757350
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摘要: The growing demand for both performance and battery life in portable consumer electronics requires SoCs power management circuits to be small, efficient, dynamically powerful. Dynamic voltage scaling (DVS) can help achieve these goals load circuits, though generally at the expense of increased DC-DC converter size (through use external inductors) or loss linear regulation). While switched-capacitor (SC) converters offer conversion small fully integrated form factors [1-5], their efficiencies are only high discrete ratios between input output voltages. To increase an SC efficiency across its range, multiple utilized realize a finer resolution. For instance, many employ handful [1-4]. However, more necessary wide range DVS, as otherwise fall by than 20% unloaded Unfortunately, increasing number beyond using standard topologies significantly components, escalating complexity adding losses additional switching elements. overcome this, successive approximation (SAR) topology was proposed [6] which cascades several 2:1 stages provide large with minimal hardware overhead. cascading introduces cascaded losses, limiting overall efficiency. example, minimum Rout is 30X similar ratio Series-Parallel same silicon area. Additionally, current density limited that single stage, capacitance utilization low ratios.