Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes

作者: Ning Chen , Yongmei Dai , Zhiyuan Yan

DOI: 10.1109/SIPS.2006.352585

关键词: Parallel computingQuantization (signal processing)Parity bitComputer scienceDecoding methodsSum product decodingLow-density parity-check code

摘要: In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization efficiency, parity check pipelined access to memory are utilized. Impacts of different node update algorithms quantization schemes studied. FPGA implementation our proposed for a (1536, 768) (3, 6)-regular QC LDPC code can achieve an estimated 61 Mbps decoding at SNR= 4.5 dB. Finally, noncoherent OSP decoder, which does not always satisfy the data dependency constraints, is that maximum gain 2 achieved all codes.

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