Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process

摘要: An improved planarization process for a trench dielectric is presented. A shallow isolation structure formed into the semiconductor substrate. thin oxide layer grown upon floor and sidewalls, then dielectric, preferably TEOS deposited using chemical-vapor deposition CVD process, The upper surface of conforms to underlying contour defined by Subsequent device formation requires substantially planar semiconductor. Conventionally, combination masking etching are used, prior chemical-mechanical polishing ("CMP"), aid process. extra steps add cost unnecessary complexity alternative proposed which uses hydrogen silsequioxane-based flowable ("HSQ"). HSQ spin-on conformal in liquid form. After heated causes it reflow produce surface. parameters (such as temperature time) chosen so that has polish rate approximately equal dielectric. ("CMP") used entirely remove portion exterior trenches. Since polished at same after level