On Two-Phase Switched-Capacitor Multipliers With Minimum Circuit Area
作者： Toru Tanzawa
DOI: 10.1109/TCSI.2010.2046958
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摘要: This paper compares the performance among two-phase switched-capacitor multipliers to identify optimum topology with smallest circuit area. The number of stages is calculated for every multiplier minimize area under condition that a certain current outputted given output voltage. Then, areas serial-parallel, linear (LIN), Fibonacci, and 2N are compared. Results show LIN cell best integration because total capacitor highest efficiency assumption parasitic capacitance not smaller than 10% capacitance, Fibonacci discrete application minimum components moderate larger 1% capacitance.
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sci-hub.se 参考文章(26)
M.S. Makowski, D. Maksimovic, Performance limits of switched-capacitor DC-DC converters power electronics specialists conference. ,vol. 2, pp. 1215- 1221 ,(1995) , 10.1109/PESC.1995.474969
L. Gobbi, A. Cabrini, G. Torelli, Impact of parasitic elements on CMOS charge pumps: a numerical analysis international symposium on circuits and systems. pp. 3125- 3128 ,(2006) , 10.1109/ISCAS.2006.1693287
A.H. Falkner, Generalised Cockcroft-Walton voltage multipliers Electronics Letters. ,vol. 9, pp. 585- 586 ,(1973) , 10.1049/EL:19730433
T.M. Van Breussegem, M. Wens, E. Geukens, D. Geys, M.S.J. Steyaert, Area-driven optimisation of switched-capacitor DC/DC converters Electronics Letters. ,vol. 44, pp. 1488- 1490 ,(2008) , 10.1049/EL:20081687
Experiments with High Velocity Positive Ions. (I) Further Developments in the Method of Obtaining High Velocity Positive Ions Proceedings of The Royal Society A: Mathematical, Physical and Engineering Sciences. ,vol. 136, pp. 619- 630 ,(1932) , 10.1098/RSPA.1932.0107
A. Umezawa, S. Atsumi, M. Kuriyama, H. Banba, K. Imamiya, K. Naruke, S. Yamada, E. Obi, M. Oshikiri, T. Suzuki, S. Tanaka, A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure IEEE Journal of Solid-state Circuits. ,vol. 27, pp. 1540- 1546 ,(1992) , 10.1109/4.165334
J.S. Brugler, Theoretical performance of voltage multiplier circuits IEEE Journal of Solid-state Circuits. ,vol. 6, pp. 132- 135 ,(1971) , 10.1109/JSSC.1971.1049670
A. Cabrini, L. Gobbi, G. Torelli, Voltage Gain Analysis of Integrated Fibonacci-Like Charge Pumps for Low Power Applications IEEE Transactions on Circuits and Systems Ii-express Briefs. ,vol. 54, pp. 929- 933 ,(2007) , 10.1109/TCSII.2007.904156
Feng Su, Wing-Hung Ki, Design Strategy for Step-Up Charge Pumps With Variable Integer Conversion Ratios IEEE Transactions on Circuits and Systems Ii-express Briefs. ,vol. 54, pp. 417- 421 ,(2007) , 10.1109/TCSII.2006.890405
Michael D. Seeman, Seth R. Sanders, Analysis and Optimization of Switched-Capacitor DC–DC Converters IEEE Transactions on Power Electronics. ,vol. 23, pp. 841- 851 ,(2008) , 10.1109/TPEL.2007.915182