A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders
作者： S. Bates , G. Block
DOI: 10.1109/ISCAS.2005.1464593
关键词:
摘要: Low-density parity-check convolutional codes complement their popular block-oriented counterparts and may be more suitable in certain communication applications. These include streaming voice video packet switching networks. In this paper we introduce these propose a memory-based decoder architecture that is well suited for implementation on field-programmable gate arrays. We present an overview of the demonstrate its efficiency over register-based architectures. then discuss realization can trade performance throughput achieve up to 120 Mb/s information BER as low 2 /spl times/ 10/sup -6/ at Eb/Nq 3 dB Altera Stratix FPGA. For first-generation compares favorable with current implementations.
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