A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology
作者： Mohammad Asyaei
DOI: 10.1016/J.VLSI.2015.06.003
关键词:
摘要: In this paper, a new leakage-tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for wide fan-in gates. The main idea in the proposed using sense amplifier sensing difference between voltages across pull down network (PDN). This strategy provides correct output. technique, therefore, voltage swing of dynamic node can be reduced to decrease caused by heavy switching capacitance simulation provided with 64-bit OR gates 90nm CMOS technology model. results are compared that standard circuits at same delay, 35% reduction 2.31× noise-immunity improvement observed. A technique gates.Difference used generate output.The decreases leakage increases immunity.The superior existing designs especially
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