A new low-power dynamic circuit for wide fan-in gates
作者： Mohammad Asyaei
DOI: 10.1016/J.VLSI.2017.10.010
关键词: Register file 、 Computer science 、 Fan-in 、 Electronic engineering 、 Noise margin 、 CMOS 、 Power (physics) 、 OR gate 、 Process corners 、 Voltage
摘要: In this paper, a new dynamic circuit is proposed to reduce the power consumption of wide fan-in gates. Since voltage difference across pull-down network determines output in circuit, swing on can be lowered decrease dramatically increasing Wide OR gates are designed and simulated using domino 90nm CMOS technology. Simulation results exhibit up 2.62X improvement noise immunity 44% reduction compared conventional circuits at same delay. Moreover, 2-read, 1-write ported 64-word 32-bit/word register file circuit. The Register low-Vth model all process corners. shows 25% 32% speed for comparison with margin floor. A low-power gates.In between voltages pull down used provide voltage.The reduced by lowering network.The superior existing designs especially
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