MOSFET structure with ultra-low K spacer
作者： Philip J. Oldiges , Christy S. Tyberg , Ghavam G. Shahidi , Elbert E. Huang , Xinlin Wang
DOI:
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摘要: Disclosed is a MOSFET structure and method of fabricating the that incorporates multi-layer sidewall spacer to suppress parasitic overlap capacitance between gate conductor source/drain extensions without degrading drive current and, thereby, effecting overall performance. In one embodiment, formed with gap layer having dielectric constant equal permeable low-K (e.g., less than 3.5) layer. another first L-shaped permittivity value approximately three second Either embodiment may also have third nitride or oxide This provides increased structural integrity.
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