Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization

摘要: With aggressive technology scaling in nanometer regime, a significant fraction of dynamic power is consumed the clock network due to its high switching activity. Clock networks are typically synthesized and routed optimize for zero skew. However, skew optimization often accompanied with routing overhead which increases net capacitance thereby consuming more power. In this paper, we propose bounded buffer tree resynthesis algorithm after has been routed. Our restricts designs within specified margin from original skew, does not introduce any additional Design Rule Check (DRC) violation. Experimental results on industrial designs, by an tool, have demonstrated that our approach can achieve average reduction 5.6% 3.5% respectively marginal