BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation

摘要: In this paper, we present BCDL (Balanced Cell-based Dual-rail Logic), a new counter-measure against Side Channel Attacks (SCA) on cryptoprocessors implementing symmetrical algorithms FPGA. is DPL (Dual-rail Precharge which aims at overcoming most of the usual vulnerabilities such counter-measures, by using specific synchronization schemes, while maintaining reasonable complexity. We compare our architecture in terms complexity, performances and easiness to design with other DPLs (WDDL, IWDDL, MDPL, iMDPL, STTL, DRSL, SecLib). It shown that can be optimized achieve higher than any (more 1/2 times nominal data rate) an affordable Finally, implement AES FPGA its robustness DPA number Measurements To Disclosure (MTD) required find key regards unprotected AES. observed SCA implementation failed for 150,000 power consumption traces represents gain greater 20 w.r.t. version. Moreover fault attack study has pointed out natural resistance simple faults attacks.