Controlling depth and latency of exit of a virtual processor's idle state in a power management environment
作者： Randal C. Swanberg , Karthick Rajamani , Freeman L. Rawson , Naresh Nayar , Christopher Francois
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摘要: A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit virtual processor's idle state. virtualization layer generates cede setting information (CLSI) data. Responsive to booting logical partition, the communicates CLSI an operating (OS) partition. The OS determines, based on data, particular state processor under control OS. calling layer, assigning wake-up characteristics processor.
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