作者: Naozumi Morino , Kazuo Sakamoto , Shunsuke Toyoshima , Takahiro Hayashi , Kazuo Tanaka
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摘要: The present invention has for its purpose to provide a technique capable of reducing planar dimension the semiconductor device. An input/output circuit is formed over substrate, grounding wiring and power supply pass circuit, conductive layer bonding pad thereover. MISFET elements in nMISFET forming region pMISFET region, resistance element regions diode functioning as protective elements. A connected positioned under pulled out pulling-out between be layer.