Semiconductor device with output circuit and pad arrangements

作者: Naozumi Morino , Kazuo Sakamoto , Shunsuke Toyoshima , Takahiro Hayashi , Kazuo Tanaka

DOI:

关键词:

摘要: The present invention has for its purpose to provide a technique capable of reducing planar dimension the semiconductor device. An input/output circuit is formed over substrate, grounding wiring and power supply pass circuit, conductive layer bonding pad thereover. MISFET elements in nMISFET forming region pMISFET region, resistance element regions diode functioning as protective elements. A connected positioned under pulled out pulling-out between be layer.

参考文章(11)
Susan H. Downey, Harold A. Downey, James W. Miller, Integrated circuit die I/O cells ,(2003)
Naozumi Morino, Kazuo Sakamoto, Shunsuke Toyoshima, Takahiro Hayashi, Kazuo Tanaka, Semiconductor devices with output circuit and pad ,(2013)
良 山縣, Tetsuya Takahashi, Makoto Yamagata, 徹也 ▲高▼橋, Semiconductor integrated-circuit device ,(1997)
Takahashi Katsuhiko, SEMICONDUCTOR INTEGRATED CIRCUIT ,(1998)
Morishita Yasuyuki, Semiconductor integrated circuit ,(2005)