Stacked via-stud with improved reliability in copper metallurgy

摘要: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level layer of dielectric material over substrate, the comprising dense for passivating devices and local interconnects underneath; multiple layers formed above material, each at least low-k material; and, set stacked via-studs in layers, said via studs interconnecting one or more patterned conductive structures, cantilever material. The interconnection levels includes soft wherein are within to increase resistance thermal fatigue crack formation. In embodiment, is provided with cantilever, such that cantilevers interwoven by connecting on bulk portion conductor line adjacent interconnection, thereby increasing flexibility between levels.